1. Field of Invention
This invention relates to direct digital frequency synthesizers and the implementation of numerically controlled digital oscillators. Specifically, the invention consists of a new and improved technique which generates sinusoids digitally.
2. Discussion of Prior Art
An attractive alternative to frequency synthesis is a digital or sampled technique. The digital frequency synthesis approach employs a stable source frequency to define sampling times at which digital sinusoidal sample values are produced. These samples are converted from digital to analog format and smoothed in time by some realizable linear filter to produce analog frequency signals. The primary building block for this approach is the direct digital synthesizer or DDS. A DDS typically consists of a phase accumulator and a sine function lookup table. The input to the phase accumulator is a frequency control word which determines the periodicity of the phase accumulator. The phase accumulator is updated to a digital sine or cosine sample using the sine or cosine function lookup table. This output is then converted to an analog signal using a digital to analog converter.
Since its inception, previous inventors have created several types of improvements conceived to improve the resolution, the reduction of spurious signal components, fundamental fidelity, and reduce circuit complexity in direct digital synthesizers.
U.S. Pat. No. 5,144,571 (Direct Digital Synthesizer with Feedback Shift Register) to Thong (1992) discloses a DDS architecture which employs a linear feedback shift register used as a counter. The output of the linear feedback shift register is decoded to provide a control signal to control logic which then loads one of a multiple of selectable input frequency control words to the phase accumulator of the DDS. This process affects the overall frequency and phase of the periodic output waveform. The primary focus of this invention involves an improved device for providing a programmable frequency index to effect phase changes in the output waveform, but does not propose any innovation in increasing the final output signal frequency beyond that provided means provided in the traditional DDS architecture.
U.S. Pat. No. 5,128,623 (Direct Digital Synthesizer/Direct Analog Synthesizer Hybrid Frequency Synthesizer) to Gilmore (1992) discloses a digital/analog hybrid frequency synthesizer having a direct digital synthesizer and a bank of analog input frequency signals separated by fixed frequency intervals. The desired output signal is then generated by mixing the appropriate analog input signal and the direct digital synthesizer output. The principle focus of this invention involves a device to generate a frequency signal through the use of a DDS with analog frequency conversion rather than proposing a specific change to the DDS architecture.
U.S. Pat. No. 5,063,361 (Direct Digital Synthesizer) to Schindler and Smith (1991) discloses a DDS architecture which includes a pair of phase shifter channels with inputs and outputs coupled with radio frequency (RF) make before break switches which provides smoother phase advances and eliminates fly-back transitions to reduce excess noise power in the output. As with the previous patents, this invention proposes the use of a DDS within a network of analog RF phase shifters designed to improve output waveform transitions rather than proposing a specific change to the DDS architecture.
U.S. Pat. No. 5,045,817 (FM Deviation Control of Direct Digital Synthesizer) to Sheller (1991) discloses a direct digital synthesizer which is employed for frequency modulation using bit shifting of the frequency control word and minor adjustment of the system clock to obtain finer resolution in setting frequency modulation (FM) deviation. The principle focus of this invention involves a novel device for employing the standard DDS architecture to improve tuning resolution and does not propose a specific change to the DDS architecture.
U.S. Pat. No. 5,031,131 (Direct Digital Synthesizer) to Mikos (1991) discloses a direct digital synthesizer architecture with a pipelined phase accumulator to increase speed which includes several on-chip digital to analog converters, multiple look-up tables with differing phase spacing between addresses with a selector to best select the look-up table which provides optimum performance, and also possibly some multiple additional look-up tables for the correction of the output waveform. This invention proposes a unique combination of on-chip features which provide flexibility to the user but does not effect a significant change to the DDS architecture.
U.S. Pat. No. 5,014,231 (Randomized Digital/Analog Converter Direct Digital Synthesizer) to Gould et al (1991) discloses a sine output or phase interpolation direct digital synthesizer for use in satellite programs having a random or pseudorandom code generator for summing a random digital word whose value ranges from zero to just under the least significant bit of a digital to analog converter, with the current register value normally sent to the converter for reducing the spurious sidebands associated with the finite resolution of the converter. By controlling the converter in this manner, the spurious sidebands are reduced by randomization of the periodic behavior associated with the truncation process while lowering total phase noise. Reduction of spurious phase sidebands by conversion to broadband phase noise is accomplished using a pseudo noise (PN) code generator to produce an additive term to the phase accumulator output with magnitude between zero and the least significant bit (LSB) with the purpose of randomizing the coherent phase noise. The truncated sum and carry are processed separately. The truncated sum is used to address the lookup table. The carry pulse is delayed by an amount proportional to the truncated sum and then added back to the phase accumulator input. This patent proposes a specific change to the DDS architecture designed to improve spurious signal performance and does not propose any innovations involving power and/or complexity reduction while generating higher output signal frequency.
U.S. Pat. No. 5,010,506 (Spurious Level Reduction and Control Method for Direct Digital Synthesizers) to Hrncirik (1991) discloses a direct digital synthesizer which has a select input at the phase accumulator which detects when power disruption or frequency changes have occurred. Upon restoration of power or change to a new frequency, the phase accumulator employs the select input latch in a predetermined initial phase and thereafter reverting to a nominal control word for operation to accomplish an overall reduction in the spurious output signal level. As with the previous patent, this invention proposes a specific change to the DDS architecture designed to improve spurious signal performance but does not propose any innovations involving power and/or complexity reduction while generating higher output signal frequency.
U.S. Pat. No. 4,998,072 (High Resolution Direct Digital Synthesizer) to Sheffer (1991) discloses a direct digital synthesizer which incorporates a device for alternately asserting two distinct phase increments, thereby achieving an effective increment value proportional to a value between these two increments. Alternating between the two increment values is controlled so the multiple fractional increment values can be achieved. The principle focus of this patent involves a change to the DDS architecture permitting finer tuning resolution and does not propose any innovation involving power and/or complexity reduction while generating higher signal frequency output.
U.S. Pat. No. 4,992,743 (Dual-Tone Direct Digital Synthesizer) to Sheffer (1991) discloses a plural-tone direct digital synthesizer comprising in combination: at least one phase accumulator which receives a clock signal input and phase increment input for producing a sequence of phase information signals, at least one phase-to-amplitude converter for producing a sequence of amplitude signals in response to this sequence of phase information signals, and a device for combining an output of an additional phase accumulator and phase-to-amplitude converter. Digital to analog conversion is then performed on these two signals which are then added using an analog summer in order to obtain spectral components of both signals. Another embodiment includes the digital summation of the two output frequencies. Yet another embodiment includes two phase accumulators with a multiplexer sharing one lookup table. The digital outputs from the lookup table are digitally summed. The novelty of this patent results from a unique combination of dual DDS function and does not involve any specific changes to the DDS architecture itself.
U.S. Pat. No. 4,975,699 (Error Reduction Method and Apparatus for a Direct Digital Synthesizer) to Frey (1990) discloses a circuit for generating an analog sine voltage from a digital phase input employing memory storing sine and cosine values and a correction value for each phase and first and second digital to analog converters (DAC). For each digital phase input, selected sine and cosine values are combined, and the result is read out to the first DAC which generates an analog sine approximation voltage. A corresponding correction value is simultaneously read out to the second DAC, whose output is scaled by an attenuator to provide a correction voltage for correcting the deviation in the output voltage of the first DAC from the ideal sine voltage value. This patent proposes a change to the DDS architecture which involves the calculation of an error correction term which is ultimately applied to the output signal external to the DDS. This patent does not propose any innovations designed specifically to reduce the power or complexity of the DDS architecture while generating high frequency output signals.
U.S. Pat. No. 4,951,237 (Direct Digital Synthesizer with Selectably Randomized Accumulator) to Essenwanger (1990) discloses a direct digital synthesizer with a phase accumulator, wherein a selected few of the low order accumulator bits are dithered by a PN number generator in order to introduce flat frequency deviation density to suppress spurious signals including those close to the output or fundamental frequency. The accumulator circuit may advantageously be sectioned into a lower order accumulator and higher order accumulator in a pipelined combination with a sine approximation output circuit wherein such a spurious signal suppression is achieved without decreasing system throughput. This patent involves a change to the DDS architecture designed to improve the spurious signal performance, but does not propose any innovation designed to increase the frequency range while reducing power and complexity.
U.S. Pat. No. 4,951,004 (Coherent Direct Digital Synthesizer) to Drucker (1990) discloses a coherent direct digital waveform synthesizer, capable of generating a waveform in response to a decimally or other non-binary related reference frequency while obtaining the advantages of the use of a binary radix phase accumulator generating binary addresses for a waveform memory. The interface between these elements include a frequency converter including a voltage controlled oscillator and a further binary radix phase accumulator in the feedback path of a phase locked loop. A binary radix related digital waveform synthesizer may thus be made to produce non-binary related frequency waveforms coherent with a non-binary radix reference frequency source, and of decimal or other non-binary radix related resolution. This patent involves the use of a DDS function to generate an output frequency which may not be related to the reference frequency in a binary sense. While the patent proposes a novel use of the DDS, it does not propose an innovation to the DDS architecture itself.
U.S. Pat. No. 4,926,130 (Synchronous Up-Conversion Direct Digital Synthesizer) to Weaver (1990) discloses a method and apparatus for generating high frequency signals, comprising generating a fundamental frequency signal over a predetermined tuning range using a direct digital synthesizer with a digital to analog converter operating at a predetermined sampling frequency and mixing the fundamental frequency with a high frequency reference signal in a mixer connected to the converter and the reference source. The reference frequency signal is provided by the reference source at a high frequency which is a multiple of the digital to analog converter sampling frequency and is the difference between a desired high frequency output and the fundamental frequency. Where desired, a low pass filter is disposed between the synthesizer and the mixer and the bandpass filter is disposed between the mixer and any output elements. A divided by N element can be connected between the reference source and the digital to analog converter to provide a sampling clock signal for the converter. In addition, the reference source can operate at even higher frequencies and a divided by M element is disposed between the reference source and both the divided by N element and the mixer. This allows the reference to be used for additional upconversion mixing with low noise at high multiples of the converter sampling frequency to achieve higher output frequencies. This patent involves a technique of synchronous upconversion which employs a DDS function to generate a higher frequency output signal. In this case, the innovation focuses on a process which uses a DDS and does not propose any specific change within the DDS architecture.
U.S. Pat. No. 4,809,205 (Digital Sine Conversion Circuit for Use in Direct Digital Synthesizers) to Freeman (1989) discloses a technique to reduce the size, power and speed constraints in a direct digital synthesizer by constructing the read only memory (ROM) sine table lookup with two smaller "primary" and "secondary" amplitude ROMs and a third smaller amplitude "correction" ROM. The primary ROM provides a coarse approximation to sine by quadrant. This patent involves an innovation associated with the implementation of the lookup table function and does not propose any innovation which increases the desired output signal frequency without a significant power and complexity increase.
Additionally, other previous inventors have created techniques which involve the generation of high frequency sine waves which employ a combination of analog phase locked loops (PLLs) and a direct digital synthesizer.
U.S. Pat. No. 5,184,092 (Phase-Locked Loop Frequency Tracking Device Including a Direct Digital Synthesizer) to McNab et al (1993) discloses an invention which consists of a phase-locked loop that uses a standard DDS. In this patent, a frequency control word to the DDS provides coarse resolution in frequency tuning while the error signal of the loop is used to drive a voltage controlled oscillator (VCO) which is used as the system clock for the DDS to provide finer tuning resolution than conventional PLL designs which incorporate a DDS. The principal embodiment also includes a programmable counter for sweeping the initial frequency with a digital limiter for limiting the sweep range.
U.S. Pat. No. 5,028,887 (Direct Digital Synthesizer Driven Phase Lock Loop Frequency Synthesizer with Hard Limiter) to Gilmore (1991) discloses a frequency synthesizer which uses a direct digital synthesizer to generate a reference signal in a phase lock loop that is compared against the desired signal divided by N to generate an error signal for the VCO of the phase lock loop in one embodiment. In another embodiment, the direct digital synthesizer is directly in the feedback loop and receives a frequency control word proportional to the loop error signal. Amplitude limiting is performed upon the DDS output signal. The DDS generates an accurate periodic signal of a frequency selected from a plurality of reference frequencies. A PLL receives the DDS generated reference signal and a divide by N signal for generating an output signal at a frequency determined by the divide by N signal. The frequency resolution of the PLL is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the PLL. An input reference frequency signal is provided to the PLL with the DDS clock signal provided as a function of the PLL output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference, the number of bits in the digital word of the frequency control signal, and the DDS step size as determined by the frequency control signal.
All of these inventions focus primarily upon the use of a DDS in a phase lock loop rather than proposing improvements to the DDS architecture itself.